This invention relates to a non-volatile semiconductor memory device, in particular, a writing method of a non-volatile semiconductor memory device having a memory cell unit constituted of a plurality of memory cells which are connected to each other and each have a FETMOS structure.
In recent years, there has been developed a non-volatile semiconductor memory device wherein one memory cell unit constituted of a plurality of electrically rewritable EEPROM cells is connected to a data line. According to the non-volatile semiconductor memory device having such a structure, the number of contacts of the cells to the data line can be reduced, thereby the integration density can be increased.
In such a device, one memory cell has a FETMOS structure provided with a floating gate and a control gate formed on a semiconductor substrate so as to hold an insulating film therebetween. Adjacent memory cells are connected in series so as to share source and drain electrodes, thereby constitute a NAND cell. A memory cell array is attained by arranging a plurality of such NAND cells in matrix.
The drain electrode located on the side of one terminal of each of the NAND cells arranged in the column direction of the cell array is connected to a bit line via a selective transistor having a selective gate, and the source electrode located on the side of another one terminal of each of the NAND cells connected to a common source line via a selective transistor having a selective gate. The control gates and selective gates of the memory cells are respectively connected in common, as a control gate line (word line) and a selective gate line, in a row direction of the memory cell array.
On the other hand, a voltage applied to the bit line and a voltage applied to the gate of the selective transistor have been lowered in recent years in accordance with the decrease of an external power supply voltage Vcc. Accordingly, a voltage transferred in data writing to the diffusion layer of the memory cell is lowered, thereby a writing error may easily occur.
The operation of the above-mentioned NAND cell will be described later in detail. If a voltage applied to a non-write bit line is lowered, thereby the selective transistor which is connected to a non-select bit line and should be cut-off cannot be easily cut-off. Further, when an element isolation film is formed by the STI (Shallow Trench Isolation), an impurity concentration of a channel region is lowered in comparing with that of the device having an element isolation film formed by a LOCOS (Local Oxidation of Silicon), thereby the backgating effect of the selected transistor is decreased. As a result, the cut-off of the selective transistor is made to be difficult more and more, thereby a writing error will easily occur.